CSCI 461: Computer Architectures

Course Agenda (Spring 2024)

Class	Date	Topics covered in class
1	Wed 1/24	Course logistics, Boolean functions, truth tables, eqivalence.
2	Fri 1/26	Properties of Boolean algebra, SOP and POS forms, converting SOP into POS, intro to computational completeness, Classes T0 and T1.
3	Mon 1/29	Classes S L M, theorem of Post on computational completeness.
4	Tue 1/30	Intro to logic gates, electrical principles of logic gates, range of digital signals, the forbidden range, real gates and their parameters.
5	Wed 1/31	Multiplexor design and demultiplexor, application of multiplexors for implementing Boolean functions, implementing Boolean functions with decoders, intro to PLA.
6	Fri 2/2	PLA implementation of a full adder, minimization of Boolean functions with Karnough maps.
7	Mon 2/5	The don't care entries and their use, design of a 2x2 bit divider, hardware design steps, delays in digital circuits.
8	Tue 2/6	Intro to finite state machines (FSM), SR flip-flops. master-slave edge-triggered flip-flop design.
9	Wed 2/7	Design of turn on/off switch FSM, FSM for a mod 4 counter.
10	Fri 2/9	The stream processing FSM.
11	Mon 2/12	Design of an FSM for a vending machine.
12	Tue 2/13	Tri-state buffers, shifting registers with parallel and sequential load, the notion of ISA, examples of various computer architectures and corresponding assembly languages.
13	Wed 2/14	Three types of instructions in assembly languages and the corresponding hardware components involved, examples.
14	Fri 2/16	4- and 3-address computers, 2-, 1-, and 0-address computers, addressing modes, intro to SRC.
15	Mon 2/19	The SRC computer and its instruction set, general SRC instruction format, load-store and arithmetic instructions and their binary encodings, discussion on the branch instructions, programming the conditional branches in SRC, handling labels in the code, accessing the symbolic variables, .org and .equ assembler instruction, a program for computing the absolute value of a variable and its encoding in binary.
16	Tue 2/20	Basics of RTN, register-to-register transfers in the SRC architecture, wired AND, microcode, time-diagrams of the strobe and gate signals, the overall SRC structure.
17	Wed 2/21	RTNs and implementation of arithmetic, conditional jump, and shift instructions.
18	Fri 2/23	SRC register file and its control signals (Fig. 4.4).
19	Mon 2/26	Extracting and sign-extending the constants c1 and c2 from the instruction register IR (Fig. 4.5), The SRC memory interface, SRC ALU registers and inner structure.
20	Tue 2/27	Control signals for implementation of various ALU operations.
21	Wed 2/28	Implementation of shifts and conditional jumps in SRC, SRC clocking logic, design of the control unit.
22	Fri 3/1	A 2-bus architecture, speed-up by using two buses, a 3-bus design.
23	Mon 3/4	Interrupts and exceptions in SRC, intro to pipelined architecture, instruction and pipeline states.
24	Tue 3/5	Dependencies between various states and instructions, pipeline for the ALU instructions, pipelines for load/store and branch instructions.
25	Wed 3/6	Pipeline for branch instructions, combined pipeline for all supported instructions.
26	Fri 3/8	Details on the combined pipeline for all supporting instructions.
	Mon 3/11	Spring break
	Tue 3/12	Spring break
	Wed 3/13	Spring break
	Fri 3/15	Spring break
27	Mon 3/18	Instruction and data hazards, instruction dependencies, stalling the pipeline approaches, pipeline stalls detection, bubble insertion.
28	Tue 3/19	Dual-pipeline SRC, running the Fibonacci program on it, forwarding paths in the dual-pipeline.
29	Wed 3/20	Microprogramming approach to the SRC control unit, review of Chapter 5.
30	Fri 3/22	Approaches to represent negative numbers, radix and diminished complements, relationships between the complements, arithmetic shifts left of signed and unsigned binary numbers.
31	Mon 3/25	Arithmetic shifts right of signed and unsigned binary numbers and its relations to dividing the numbers by 2, adding and subtracting numbers, detecting an overflow.
32	Tue 3/26	Matrix multiplier design, delays in the matrix multiplier and its complexity in terms of gates, multiplier based on an adder and shift register, handling negative numbers in multiplication, multiplication of binary signed integers, example of signed multiplication.
33	Wed 3/27	Approaches to the binary division, the divider based on a shift register, the matrix divider, implementation of branches.
	Fri 3/29	No class (Good Friday)
34	Mon 4/1	Comments on Assignment 5, Barrel shifter, Barrel shifter with a logarithmic number of levels, general CPU structure.
35	Tue 4/2	Intro to floating-point numbers, adding the FP numbers, alignment and rounding-off, multiplication and division of FP numbers, general FPU structure.
36	Wed 4/3	Intro to memory and its parameters, storing a single bit by using RS flip-flops, memory organization for working with bytes, implementation of memory addresses with multiplexors, 64Kx1 and 16Kx4 RAM chip structure, Matrix and tree decoders.
37	Fri 4/5	RAM cells based on inverters. static RAM R/W operations, dynamic RAM cell and chip organization,
38	Mon 4/8	DRAM R/W cycles, ROM chips and types. Memory boards and modules, word assembly from narrow chips, increasing the memory size (a 1-dim iand 2-dim approach),
39	Tue 4/9	increasing the memory size: a 3-dim DRAM array, memory module interface and internal structure, accessing the values located in consecutive memory addresses, intro to the virtual memory.
40	Wed 4/10	Paging and segmentation approaches to translate the virtual addresses, primary and secondary memory, the hit and miss ratio, the memory access time, the associative cache architecture, replacement strategy, search for a tag.
41	Fri 4/12	Direct mapped cache and the corresponding hardware, 2-way set-associative cache, the Intel Pentium cache. cache read/write policies, Intro to virtual memory, segmentation and paging, Intel 8086 segmentation scheme, memory management by paging, virtual address translation of pages in MMU.
42	Mon 4/15	MMU algorithm for data access, Intro to memory-mapped I/O, programmed I/O, programmed I/O device interface structure.
43	Tue 4/16	Programmed I/O device drivers using polling approach, SRC hardware interrupt support, Programmed I/O device drivers using polling approach, SRC hardware interrupt support, ISR for keyboard input.
44	Wed 4/17	Implementation of interrupts in SRC, handling the interrupt priorities, hardware implementation of daisy chain, interrupt masks, prioritized interrupt controller.
	Fri 4/19	No class
45	Mon 4/22	Details on DMA implementation for TI MSP430 microcontroller and EFM32, interrupt tables for MSP430 and ARM, error detection and correction principles: the data transmission model, the code distance, parity checking, error detection and error correction technique, code redundancy.
46	Tue 4/23	Encoding and decoding messages with Hamming code and SECDED, handling different types of errors.
47	Wed 4/24	CRC checking, review of Chapter 8, Hardware aspects of various magnetic discs and CDROMs.
48	Fri 4/26	Video monitors, architecture of character-based displays.
49	Mon 4/29	Printer hardware, A-to-D and D-to-A converters basics.
50	Tue 4/30	SAR ADCs, limiting factors and error sources of ADCs, review of Chapter 9.
51	Wed 5/1	Demo of hardware CRC support, using ADC and PWM to control LED brightness, overview of storage media hardware.
52	Fri 5/3	Physical link waveforms, network topologies, communication with modems, details of RS-232, Baud rate.
53	Mon 5/6	LAN and CSMA/CD algorithm, Ethernet packet structure, comparison of USB and FireWire, Internet names and addresses, TCP/IP protocol stack, Internet routing, subnets, intro to CISC and RISC architectures, the Motorolla MC68000 processor.
54	Tue 5/7	Introduction to the Motorola assembly language: addressing modes. 68000 CPU instruction formats, load and store instructions, arithmetic instructions.
55	Wed 5/8	Branch instructions for Motorola 68000 microprocessor, sample programs, encoding encoding of arithmetic instructions, supplementary words in instructions and their structure, the `DBcc` instruction and its logic, a sample program for finding the end of line character (CR) in a string and its binary encoding, subroutine linkage in 68000, encoding 2 sample programs in binary.
56	Fri 5/10	Intro to SPARC architecture: registers set, instruction formats, discussion on a RISC computers, SPARC addressing modes, subroutine linkage in SPARC, delay slots for the branch instructions, encoding a sample SPARC program in binary.