CSCI 461: Computer Architectures

Course Agenda (Spring 2026)

ClassDateTopics covered in class
1Wed
1/21
Course logistics, Boolean functions, truth tables, eqivalence.
2Fri
1/23
Properties of Boolean algebra, SOP and POS forms, converting SOP into POS, intro to computational completeness.
3Mon
1/26
Classes T0 T1 S M L, theorem of Post on computational completeness, intro to logic gates, electrical principles of logic gates, range of digital signals, the forbidden range, real gates and their parameters.
4Tue
1/27
Multiplexor design and demultiplexor, application of multiplexors for implementing Boolean functions, implementing Boolean functions with decoders, intro to PLA.
5Wed
1/28
PLA implementation of a full adder, minimization of Boolean functions with Karnough maps.
6Fri
1/30
The don't care entries and their use, design of a 2x2 bit divider, hardware design steps, delays in digital circuits.
7Mon
2/2
Intro to finite state machines (FSM), SR flip-flops, master-slave edge-triggered flip-flop design, FSM for a mod 4 counter.
8Tue
2/3
Design of turn on/off switch FSM, The stream processing FSM.
9Wed
2/4
Design of an FSM for a vending machine, Tri-state buffers.
10Fri
2/6
Shift registers with parallel and sequential load, the notion of ISA, examples of various computer architectures and corresponding assembly languages.
11Mon
2/9
Three types of instructions in assembly languages and the corresponding hardware components involved, examples.
12Tue
2/10
4- and 3-address computers, 2-, 1-, and 0-address computers, addressing modes, intro to SRC.
13Wed
2/11
The SRC computer and its instruction set, general SRC instruction format, load-store and arithmetic instructions and their binary encodings, discussion on the branch instructions, programming the conditional branches in SRC, handling labels in the code, accessing the symbolic variables, .org and .equ assembler instruction, a program for computing the absolute value of a variable and its encoding in binary.
14Fri
2/13
Basics of RTN, register-to-register transfers in the SRC architecture, wired AND, microcode, time-diagrams of the strobe and gate signals, the overall SRC structure.