Sometimes it is needed to construct a fast decimal counter having only a binary (mod 16) counter handy. The theory is trivial - one just needs to reset the counter upon receiving the 10-th clock pulse. Most advises on the Web suggest to catch the output combination 1010 (decimal 10) by using a 2-input NAND gate and use this signal for the counter reset.
To implement a fast counter synchronous binary counters should be used. Such devices as a rule have a decent control logic. In particular, the reset can be done by applying a (usually asynchronous) counter reset or by enabling a (usually synchronous) parallel load of 0000. I implemented the second way. In this case, however, since the parallel load is a synchronous signal, in order it to occur at the 10-th clock pulse one should issue it as soon as the counter reaches the state 1001.
The circuit below is based on 74LV161A synchronous binary counter whose clock frequency can be as high as 220MHz by powering it from 5V. Another chip consists of a single 2-input NAND gate. The oscillogram on the right proves correctness of the design. The bottom graph is the input signal which the top one is taken from the output. As it follows from the graphs, its period is equal to 10 input periods.
| Schematic | Layout | Oscillogram | ||
The counter was tested by diving input frequency of 150MHz. In a real word application it would be beneficial to add a buffer at the counter output. The outputs of SN74LV161A are pretty sensible to capacitive load. The chip stops working even by attaching scope cables, so I had to use an integrated voltage divider to resolve the problem (which noticeably reduces the scope input capacitance).
| Dividing 150MHz | Input signal | |
Last modified:Mon, Jan 23, 2023.