Static Timing Analysis

Project : Metro
Build Time : 05/19/17 10:24:46
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
Clock_SPK(FFB) Clock_SPK(FFB) 500.000 kHz 500.000 kHz N/A
CyHFCLK CyHFCLK 6.000 MHz 6.000 MHz N/A
Clock_SPK CyHFCLK 500.000 kHz 500.000 kHz N/A
Clock_Tempo CyHFCLK 1.000 MHz 1.000 MHz 43.057 MHz
Clock_Deb CyHFCLK 50.000  Hz 50.000  Hz 141.283 MHz
I2C_SCBCLK CyHFCLK 2.000 MHz 2.000 MHz N/A
Clock_Dec CyHFCLK 1.000 kHz 1.000 kHz 38.193 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 6.000 MHz 6.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 6.000 MHz 6.000 MHz N/A
CySYSCLK CySYSCLK 6.000 MHz 6.000 MHz N/A
I2C_SCBCLK(FFB) I2C_SCBCLK(FFB) 2.000 MHz 2.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 2e+007ns(50  Hz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Debouncer:DEBOUNCER[0]:d_sync_1\/q Net_709/main_1 141.283 MHz 7.078 19999992.922
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(0,1) 1 \Debouncer:DEBOUNCER[0]:d_sync_1\ \Debouncer:DEBOUNCER[0]:d_sync_1\/clock_0 \Debouncer:DEBOUNCER[0]:d_sync_1\/q 1.250
Route 1 \Debouncer:DEBOUNCER[0]:d_sync_1\ \Debouncer:DEBOUNCER[0]:d_sync_1\/q Net_709/main_1 2.318
macrocell23 U(0,1) 1 Net_709 SETUP 3.510
Clock Skew 0.000
\Debouncer:DEBOUNCER[0]:d_sync_0\/q Net_709/main_0 141.623 MHz 7.061 19999992.939
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(0,1) 1 \Debouncer:DEBOUNCER[0]:d_sync_0\ \Debouncer:DEBOUNCER[0]:d_sync_0\/clock_0 \Debouncer:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \Debouncer:DEBOUNCER[0]:d_sync_0\ \Debouncer:DEBOUNCER[0]:d_sync_0\/q Net_709/main_0 2.301
macrocell23 U(0,1) 1 Net_709 SETUP 3.510
Clock Skew 0.000
\Debouncer:DEBOUNCER[0]:d_sync_0\/q \Debouncer:DEBOUNCER[0]:d_sync_1\/main_0 141.623 MHz 7.061 19999992.939
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(0,1) 1 \Debouncer:DEBOUNCER[0]:d_sync_0\ \Debouncer:DEBOUNCER[0]:d_sync_0\/clock_0 \Debouncer:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \Debouncer:DEBOUNCER[0]:d_sync_0\ \Debouncer:DEBOUNCER[0]:d_sync_0\/q \Debouncer:DEBOUNCER[0]:d_sync_1\/main_0 2.301
macrocell25 U(0,1) 1 \Debouncer:DEBOUNCER[0]:d_sync_1\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1e+006ns(1 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/z0_comb \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_0 38.193 MHz 26.183 999973.817
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\ \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/clock \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/z0_comb 3.850
Route 1 \QuadDec:Cnt8:CounterUDB:status_1\ \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/z0_comb \QuadDec:Cnt8:CounterUDB:reload\/main_1 5.156
macrocell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:reload\ \QuadDec:Cnt8:CounterUDB:reload\/main_1 \QuadDec:Cnt8:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt8:CounterUDB:reload\ \QuadDec:Cnt8:CounterUDB:reload\/q \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_0 2.307
datapathcell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/f0_comb \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_0 42.100 MHz 23.753 999976.247
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\ \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/clock \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/f0_comb 4.260
Route 1 \QuadDec:Cnt8:CounterUDB:overflow\ \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/f0_comb \QuadDec:Cnt8:CounterUDB:reload\/main_2 2.316
macrocell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:reload\ \QuadDec:Cnt8:CounterUDB:reload\/main_2 \QuadDec:Cnt8:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt8:CounterUDB:reload\ \QuadDec:Cnt8:CounterUDB:reload\/q \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_0 2.307
datapathcell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\QuadDec:Cnt8:CounterUDB:sCTRLReg:ctrlreg\/control_7 \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_1 43.044 MHz 23.232 999976.768
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:sCTRLReg:ctrlreg\ \QuadDec:Cnt8:CounterUDB:sCTRLReg:ctrlreg\/clock \QuadDec:Cnt8:CounterUDB:sCTRLReg:ctrlreg\/control_7 2.580
Route 1 \QuadDec:Cnt8:CounterUDB:control_7\ \QuadDec:Cnt8:CounterUDB:sCTRLReg:ctrlreg\/control_7 \QuadDec:Cnt8:CounterUDB:count_enable\/main_0 2.911
macrocell5 U(0,0) 1 \QuadDec:Cnt8:CounterUDB:count_enable\ \QuadDec:Cnt8:CounterUDB:count_enable\/main_0 \QuadDec:Cnt8:CounterUDB:count_enable\/q 3.350
Route 1 \QuadDec:Cnt8:CounterUDB:count_enable\ \QuadDec:Cnt8:CounterUDB:count_enable\/q \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_1 2.871
datapathcell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\QuadDec:Net_1260\/q \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_0 45.867 MHz 21.802 999978.198
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(1,1) 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/clock_0 \QuadDec:Net_1260\/q 1.250
Route 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/q \QuadDec:Cnt8:CounterUDB:reload\/main_0 3.375
macrocell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:reload\ \QuadDec:Cnt8:CounterUDB:reload\/main_0 \QuadDec:Cnt8:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt8:CounterUDB:reload\ \QuadDec:Cnt8:CounterUDB:reload\/q \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_0 2.307
datapathcell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\QuadDec:Net_1203\/q \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_1 46.162 MHz 21.663 999978.337
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,0) 1 \QuadDec:Net_1203\ \QuadDec:Net_1203\/clock_0 \QuadDec:Net_1203\/q 1.250
Route 1 \QuadDec:Net_1203\ \QuadDec:Net_1203\/q \QuadDec:Cnt8:CounterUDB:count_enable\/main_2 2.672
macrocell5 U(0,0) 1 \QuadDec:Cnt8:CounterUDB:count_enable\ \QuadDec:Cnt8:CounterUDB:count_enable\/main_2 \QuadDec:Cnt8:CounterUDB:count_enable\/q 3.350
Route 1 \QuadDec:Cnt8:CounterUDB:count_enable\ \QuadDec:Cnt8:CounterUDB:count_enable\/q \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_1 2.871
datapathcell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\QuadDec:Cnt8:CounterUDB:count_stored_i\/q \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_1 47.136 MHz 21.215 999978.785
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(0,0) 1 \QuadDec:Cnt8:CounterUDB:count_stored_i\ \QuadDec:Cnt8:CounterUDB:count_stored_i\/clock_0 \QuadDec:Cnt8:CounterUDB:count_stored_i\/q 1.250
Route 1 \QuadDec:Cnt8:CounterUDB:count_stored_i\ \QuadDec:Cnt8:CounterUDB:count_stored_i\/q \QuadDec:Cnt8:CounterUDB:count_enable\/main_1 2.224
macrocell5 U(0,0) 1 \QuadDec:Cnt8:CounterUDB:count_enable\ \QuadDec:Cnt8:CounterUDB:count_enable\/main_1 \QuadDec:Cnt8:CounterUDB:count_enable\/q 3.350
Route 1 \QuadDec:Cnt8:CounterUDB:count_enable\ \QuadDec:Cnt8:CounterUDB:count_enable\/q \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_1 2.871
datapathcell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/ce1_comb \QuadDec:Cnt8:CounterUDB:sSTSReg:stsreg\/status_0 53.804 MHz 18.586 999981.414
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\ \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/clock \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/ce1_comb 5.030
Route 1 \QuadDec:Cnt8:CounterUDB:cmp_out_i\ \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/ce1_comb \QuadDec:Cnt8:CounterUDB:status_0\/main_0 2.892
macrocell2 U(0,0) 1 \QuadDec:Cnt8:CounterUDB:status_0\ \QuadDec:Cnt8:CounterUDB:status_0\/main_0 \QuadDec:Cnt8:CounterUDB:status_0\/q 3.350
Route 1 \QuadDec:Cnt8:CounterUDB:status_0\ \QuadDec:Cnt8:CounterUDB:status_0\/q \QuadDec:Cnt8:CounterUDB:sSTSReg:stsreg\/status_0 5.744
statusicell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:sSTSReg:stsreg\ SETUP 1.570
Clock Skew 0.000
\QuadDec:Net_1260\/q \QuadDec:Net_1251\/main_7 61.087 MHz 16.370 999983.630
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(1,1) 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/clock_0 \QuadDec:Net_1260\/q 1.250
Route 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/q \QuadDec:Net_1251_split\/main_1 5.417
macrocell16 U(1,0) 1 \QuadDec:Net_1251_split\ \QuadDec:Net_1251_split\/main_1 \QuadDec:Net_1251_split\/q 3.350
Route 1 \QuadDec:Net_1251_split\ \QuadDec:Net_1251_split\/q \QuadDec:Net_1251\/main_7 2.843
macrocell11 U(1,1) 1 \QuadDec:Net_1251\ SETUP 3.510
Clock Skew 0.000
\QuadDec:Net_1251\/q \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_2 64.309 MHz 15.550 999984.450
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,1) 1 \QuadDec:Net_1251\ \QuadDec:Net_1251\/clock_0 \QuadDec:Net_1251\/q 1.250
Route 1 \QuadDec:Net_1251\ \QuadDec:Net_1251\/q \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_2 2.780
datapathcell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:sC8:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\QuadDec:Cnt8:CounterUDB:prevCompare\/q \QuadDec:Cnt8:CounterUDB:sSTSReg:stsreg\/status_0 64.943 MHz 15.398 999984.602
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(0,0) 1 \QuadDec:Cnt8:CounterUDB:prevCompare\ \QuadDec:Cnt8:CounterUDB:prevCompare\/clock_0 \QuadDec:Cnt8:CounterUDB:prevCompare\/q 1.250
Route 1 \QuadDec:Cnt8:CounterUDB:prevCompare\ \QuadDec:Cnt8:CounterUDB:prevCompare\/q \QuadDec:Cnt8:CounterUDB:status_0\/main_1 3.484
macrocell2 U(0,0) 1 \QuadDec:Cnt8:CounterUDB:status_0\ \QuadDec:Cnt8:CounterUDB:status_0\/main_1 \QuadDec:Cnt8:CounterUDB:status_0\/q 3.350
Route 1 \QuadDec:Cnt8:CounterUDB:status_0\ \QuadDec:Cnt8:CounterUDB:status_0\/q \QuadDec:Cnt8:CounterUDB:sSTSReg:stsreg\/status_0 5.744
statusicell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:sSTSReg:stsreg\ SETUP 1.570
Clock Skew 0.000
Path Delay Requirement : 1000ns(1 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer:TimerUDB:sT16:timerdp:u0\/z0 \Timer:TimerUDB:sT16:timerdp:u1\/ci 43.057 MHz 23.225 976.775
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/clock \Timer:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/z0 \Timer:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/z0i \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Timer:TimerUDB:per_zero\ \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.145
datapathcell2 U(1,0) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/co_msb \Timer:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u1\/ci 45.882 MHz 21.795 978.205
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/clock \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
Route 1 \Timer:TimerUDB:per_zero\ \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.145
datapathcell2 U(1,0) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/co_msb \Timer:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:sT16:timerdp:u1\/ci 49.356 MHz 20.261 979.739
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,0) 1 \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer:TimerUDB:control_7\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.881
datapathcell2 U(1,0) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/co_msb \Timer:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer:TimerUDB:sT16:timerdp:u0\/z0 \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 50.138 MHz 19.945 980.055
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/clock \Timer:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/z0 \Timer:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/z0i \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Timer:TimerUDB:per_zero\ \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.145
datapathcell2 U(1,0) 1 \Timer:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer:TimerUDB:sT16:timerdp:u0\/z0 \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_0 50.173 MHz 19.931 980.069
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/clock \Timer:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/z0 \Timer:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/z0i \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_0 3.131
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 54.010 MHz 18.515 981.485
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/clock \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
Route 1 \Timer:TimerUDB:per_zero\ \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.145
datapathcell2 U(1,0) 1 \Timer:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_0 54.051 MHz 18.501 981.499
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/clock \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_0 3.131
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_1 58.360 MHz 17.135 982.865
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,0) 1 \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer:TimerUDB:control_7\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_1 3.035
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 58.889 MHz 16.981 983.019
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,0) 1 \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer:TimerUDB:control_7\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.881
datapathcell2 U(1,0) 1 \Timer:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer:TimerUDB:sT16:timerdp:u0\/z0 \Timer:TimerUDB:rstSts:stsreg\/status_0 64.029 MHz 15.618 984.382
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/clock \Timer:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/z0 \Timer:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/z0i \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Timer:TimerUDB:per_zero\ \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:status_tc\/main_1 3.152
macrocell8 U(0,0) 1 \Timer:TimerUDB:status_tc\ \Timer:TimerUDB:status_tc\/main_1 \Timer:TimerUDB:status_tc\/q 3.350
Route 1 \Timer:TimerUDB:status_tc\ \Timer:TimerUDB:status_tc\/q \Timer:TimerUDB:rstSts:stsreg\/status_0 2.266
statusicell3 U(0,0) 1 \Timer:TimerUDB:rstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\Debouncer:DEBOUNCER[0]:d_sync_0\/q Net_709/main_0 3.551
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(0,1) 1 \Debouncer:DEBOUNCER[0]:d_sync_0\ \Debouncer:DEBOUNCER[0]:d_sync_0\/clock_0 \Debouncer:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \Debouncer:DEBOUNCER[0]:d_sync_0\ \Debouncer:DEBOUNCER[0]:d_sync_0\/q Net_709/main_0 2.301
macrocell23 U(0,1) 1 Net_709 HOLD 0.000
Clock Skew 0.000
\Debouncer:DEBOUNCER[0]:d_sync_0\/q \Debouncer:DEBOUNCER[0]:d_sync_1\/main_0 3.551
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(0,1) 1 \Debouncer:DEBOUNCER[0]:d_sync_0\ \Debouncer:DEBOUNCER[0]:d_sync_0\/clock_0 \Debouncer:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \Debouncer:DEBOUNCER[0]:d_sync_0\ \Debouncer:DEBOUNCER[0]:d_sync_0\/q \Debouncer:DEBOUNCER[0]:d_sync_1\/main_0 2.301
macrocell25 U(0,1) 1 \Debouncer:DEBOUNCER[0]:d_sync_1\ HOLD 0.000
Clock Skew 0.000
\Debouncer:DEBOUNCER[0]:d_sync_1\/q Net_709/main_1 3.568
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(0,1) 1 \Debouncer:DEBOUNCER[0]:d_sync_1\ \Debouncer:DEBOUNCER[0]:d_sync_1\/clock_0 \Debouncer:DEBOUNCER[0]:d_sync_1\/q 1.250
Route 1 \Debouncer:DEBOUNCER[0]:d_sync_1\ \Debouncer:DEBOUNCER[0]:d_sync_1\/q Net_709/main_1 2.318
macrocell23 U(0,1) 1 Net_709 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\QuadDec:bQuadDec:state_1\/q \QuadDec:Net_1260\/main_2 3.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(1,1) 1 \QuadDec:bQuadDec:state_1\ \QuadDec:bQuadDec:state_1\/clock_0 \QuadDec:bQuadDec:state_1\/q 1.250
Route 1 \QuadDec:bQuadDec:state_1\ \QuadDec:bQuadDec:state_1\/q \QuadDec:Net_1260\/main_2 2.290
macrocell19 U(1,1) 1 \QuadDec:Net_1260\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:state_1\/q \QuadDec:bQuadDec:error\/main_4 3.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(1,1) 1 \QuadDec:bQuadDec:state_1\ \QuadDec:bQuadDec:state_1\/clock_0 \QuadDec:bQuadDec:state_1\/q 1.250
Route 1 \QuadDec:bQuadDec:state_1\ \QuadDec:bQuadDec:state_1\/q \QuadDec:bQuadDec:error\/main_4 2.290
macrocell20 U(1,1) 1 \QuadDec:bQuadDec:error\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:state_0\/q \QuadDec:Net_1203\/main_6 3.776
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,0) 1 \QuadDec:bQuadDec:state_0\ \QuadDec:bQuadDec:state_0\/clock_0 \QuadDec:bQuadDec:state_0\/q 1.250
Route 1 \QuadDec:bQuadDec:state_0\ \QuadDec:bQuadDec:state_0\/q \QuadDec:Net_1203\/main_6 2.526
macrocell18 U(1,0) 1 \QuadDec:Net_1203\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:state_0\/q \QuadDec:bQuadDec:state_0\/main_5 3.776
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,0) 1 \QuadDec:bQuadDec:state_0\ \QuadDec:bQuadDec:state_0\/clock_0 \QuadDec:bQuadDec:state_0\/q 1.250
macrocell22 U(1,0) 1 \QuadDec:bQuadDec:state_0\ \QuadDec:bQuadDec:state_0\/q \QuadDec:bQuadDec:state_0\/main_5 2.526
macrocell22 U(1,0) 1 \QuadDec:bQuadDec:state_0\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:error\/q \QuadDec:Net_1260\/main_1 3.826
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(1,1) 1 \QuadDec:bQuadDec:error\ \QuadDec:bQuadDec:error\/clock_0 \QuadDec:bQuadDec:error\/q 1.250
Route 1 \QuadDec:bQuadDec:error\ \QuadDec:bQuadDec:error\/q \QuadDec:Net_1260\/main_1 2.576
macrocell19 U(1,1) 1 \QuadDec:Net_1260\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:error\/q \QuadDec:bQuadDec:error\/main_3 3.826
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(1,1) 1 \QuadDec:bQuadDec:error\ \QuadDec:bQuadDec:error\/clock_0 \QuadDec:bQuadDec:error\/q 1.250
macrocell20 U(1,1) 1 \QuadDec:bQuadDec:error\ \QuadDec:bQuadDec:error\/q \QuadDec:bQuadDec:error\/main_3 2.576
macrocell20 U(1,1) 1 \QuadDec:bQuadDec:error\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:error\/q \QuadDec:Net_1251\/main_4 3.832
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(1,1) 1 \QuadDec:bQuadDec:error\ \QuadDec:bQuadDec:error\/clock_0 \QuadDec:bQuadDec:error\/q 1.250
Route 1 \QuadDec:bQuadDec:error\ \QuadDec:bQuadDec:error\/q \QuadDec:Net_1251\/main_4 2.582
macrocell11 U(1,1) 1 \QuadDec:Net_1251\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:error\/q \QuadDec:bQuadDec:state_1\/main_3 3.832
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(1,1) 1 \QuadDec:bQuadDec:error\ \QuadDec:bQuadDec:error\/clock_0 \QuadDec:bQuadDec:error\/q 1.250
Route 1 \QuadDec:bQuadDec:error\ \QuadDec:bQuadDec:error\/q \QuadDec:bQuadDec:state_1\/main_3 2.582
macrocell21 U(1,1) 1 \QuadDec:bQuadDec:state_1\ HOLD 0.000
Clock Skew 0.000
\QuadDec:Net_1203\/q \QuadDec:Cnt8:CounterUDB:count_stored_i\/main_0 3.922
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,0) 1 \QuadDec:Net_1203\ \QuadDec:Net_1203\/clock_0 \QuadDec:Net_1203\/q 1.250
Route 1 \QuadDec:Net_1203\ \QuadDec:Net_1203\/q \QuadDec:Cnt8:CounterUDB:count_stored_i\/main_0 2.672
macrocell17 U(0,0) 1 \QuadDec:Cnt8:CounterUDB:count_stored_i\ HOLD 0.000
Clock Skew 0.000
\QuadDec:Net_1203\/q \QuadDec:Net_1203\/main_1 3.928
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,0) 1 \QuadDec:Net_1203\ \QuadDec:Net_1203\/clock_0 \QuadDec:Net_1203\/q 1.250
macrocell18 U(1,0) 1 \QuadDec:Net_1203\ \QuadDec:Net_1203\/q \QuadDec:Net_1203\/main_1 2.678
macrocell18 U(1,0) 1 \QuadDec:Net_1203\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Timer:TimerUDB:sT16:timerdp:u0\/co_msb \Timer:TimerUDB:sT16:timerdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/clock \Timer:TimerUDB:sT16:timerdp:u0\/co_msb 3.210
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/co_msb \Timer:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 4.921
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,0) 1 \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer:TimerUDB:control_7\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.881
datapathcell2 U(1,0) 1 \Timer:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_1 5.075
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,0) 1 \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer:TimerUDB:control_7\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_1 3.035
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_0 6.401
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/clock \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 3.270
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_0 3.131
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 6.415
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/clock \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 3.270
Route 1 \Timer:TimerUDB:per_zero\ \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.145
datapathcell2 U(1,0) 1 \Timer:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:sT16:timerdp:u0\/z0 \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_0 7.611
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/clock \Timer:TimerUDB:sT16:timerdp:u0\/z0 1.740
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/z0 \Timer:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/z0i \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_0 3.131
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:sT16:timerdp:u0\/z0 \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 7.625
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/clock \Timer:TimerUDB:sT16:timerdp:u0\/z0 1.740
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/z0 \Timer:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/z0i \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
Route 1 \Timer:TimerUDB:per_zero\ \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.145
datapathcell2 U(1,0) 1 \Timer:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:rstSts:stsreg\/status_0 8.695
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,0) 1 \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer:TimerUDB:control_7\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:status_tc\/main_0 3.039
macrocell8 U(0,0) 1 \Timer:TimerUDB:status_tc\ \Timer:TimerUDB:status_tc\/main_0 \Timer:TimerUDB:status_tc\/q 3.350
Route 1 \Timer:TimerUDB:status_tc\ \Timer:TimerUDB:status_tc\/q \Timer:TimerUDB:rstSts:stsreg\/status_0 2.266
statusicell3 U(0,0) 1 \Timer:TimerUDB:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:rstSts:stsreg\/status_0 10.038
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/clock \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 3.270
Route 1 \Timer:TimerUDB:per_zero\ \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:status_tc\/main_1 3.152
macrocell8 U(0,0) 1 \Timer:TimerUDB:status_tc\ \Timer:TimerUDB:status_tc\/main_1 \Timer:TimerUDB:status_tc\/q 3.350
Route 1 \Timer:TimerUDB:status_tc\ \Timer:TimerUDB:status_tc\/q \Timer:TimerUDB:rstSts:stsreg\/status_0 2.266
statusicell3 U(0,0) 1 \Timer:TimerUDB:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\Timer:TimerUDB:sT16:timerdp:u0\/z0 \Timer:TimerUDB:rstSts:stsreg\/status_0 11.248
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/clock \Timer:TimerUDB:sT16:timerdp:u0\/z0 1.740
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/z0 \Timer:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell3 U(0,0) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/z0i \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
Route 1 \Timer:TimerUDB:per_zero\ \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:status_tc\/main_1 3.152
macrocell8 U(0,0) 1 \Timer:TimerUDB:status_tc\ \Timer:TimerUDB:status_tc\/main_1 \Timer:TimerUDB:status_tc\/q 3.350
Route 1 \Timer:TimerUDB:status_tc\ \Timer:TimerUDB:status_tc\/q \Timer:TimerUDB:rstSts:stsreg\/status_0 2.266
statusicell3 U(0,0) 1 \Timer:TimerUDB:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
+ Input To Clock Section
+ Clock_Deb
Source Destination Delay (ns)
BUTTON(0)_PAD \Debouncer:DEBOUNCER[0]:d_sync_0\/main_1 25.931
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 BUTTON(0)_PAD BUTTON(0)_PAD BUTTON(0)/pad_in 0.000
iocell11 P2[1] 1 BUTTON(0) BUTTON(0)/pad_in BUTTON(0)/fb 16.957
Route 1 Net_713 BUTTON(0)/fb \Debouncer:DEBOUNCER[0]:d_sync_0\/main_1 5.464
macrocell24 U(0,1) 1 \Debouncer:DEBOUNCER[0]:d_sync_0\ SETUP 3.510
Clock Clock path delay 0.000
Dec_3(0)_PAD \Debouncer:DEBOUNCER[0]:d_sync_0\/main_0 22.156
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Dec_3(0)_PAD Dec_3(0)_PAD Dec_3(0)/pad_in 0.000
iocell6 P3[6] 1 Dec_3(0) Dec_3(0)/pad_in Dec_3(0)/fb 12.937
Route 1 Net_714 Dec_3(0)/fb \Debouncer:DEBOUNCER[0]:d_sync_0\/main_0 5.709
macrocell24 U(0,1) 1 \Debouncer:DEBOUNCER[0]:d_sync_0\ SETUP 3.510
Clock Clock path delay 0.000
+ Clock_Dec
Source Destination Delay (ns)
Dec_1(0)_PAD \QuadDec:bQuadDec:quad_A_filt\/main_0 19.658
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Dec_1(0)_PAD Dec_1(0)_PAD Dec_1(0)/pad_in 0.000
iocell3 P3[4] 1 Dec_1(0) Dec_1(0)/pad_in Dec_1(0)/fb 11.517
Route 1 Net_76 Dec_1(0)/fb \QuadDec:bQuadDec:quad_A_filt\/main_0 4.631
macrocell9 U(1,0) 1 \QuadDec:bQuadDec:quad_A_filt\ SETUP 3.510
Clock Clock path delay 0.000
Dec_2(0)_PAD \QuadDec:bQuadDec:quad_B_filt\/main_0 18.544
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Dec_2(0)_PAD Dec_2(0)_PAD Dec_2(0)/pad_in 0.000
iocell4 P3[5] 1 Dec_2(0) Dec_2(0)/pad_in Dec_2(0)/fb 10.397
Route 1 Net_43 Dec_2(0)/fb \QuadDec:bQuadDec:quad_B_filt\/main_0 4.637
macrocell10 U(0,0) 1 \QuadDec:bQuadDec:quad_B_filt\ SETUP 3.510
Clock Clock path delay 0.000
+ Clock To Output Section
+ Clock_SPK(FFB)
Source Destination Delay (ns)
\PWM:cy_m0s8_tcpwm_1\/line_out Spkr(0)_PAD 17.967
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,0) 1 \PWM:cy_m0s8_tcpwm_1\ \PWM:cy_m0s8_tcpwm_1\/clock \PWM:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 Net_683 \PWM:cy_m0s8_tcpwm_1\/line_out Spkr(0)/pin_input 2.587
iocell5 P3[7] 1 Spkr(0) Spkr(0)/pin_input Spkr(0)/pad_out 15.380
Route 1 Spkr(0)_PAD Spkr(0)/pad_out Spkr(0)_PAD 0.000
Clock Clock path delay 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 1e+006ns(1 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\QuadDec:Net_1260\/q \QuadDec:Cnt8:CounterUDB:sSTSReg:stsreg\/reset 215.285 MHz 4.645 999995.355
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(1,1) 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/clock_0 \QuadDec:Net_1260\/q 1.250
Route 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/q \QuadDec:Cnt8:CounterUDB:sSTSReg:stsreg\/reset 3.395
statusicell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:sSTSReg:stsreg\ RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
\QuadDec:Net_1260\/q \QuadDec:Cnt8:CounterUDB:sSTSReg:stsreg\/reset 4.645
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(1,1) 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/clock_0 \QuadDec:Net_1260\/q 1.250
Route 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/q \QuadDec:Cnt8:CounterUDB:sSTSReg:stsreg\/reset 3.395
statusicell1 U(0,1) 1 \QuadDec:Cnt8:CounterUDB:sSTSReg:stsreg\ REMOVAL 0.000
Clock Skew 0.000