Static Timing Analysis

Project : RainGauge
Build Time : 05/02/16 22:10:18
Device : CY8C4125PVI-482
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 6.000 MHz 6.000 MHz N/A
LCD_Clock CyHFCLK 3.000 MHz 3.000 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 6.000 MHz 6.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 6.000 MHz 6.000 MHz N/A
CySYSCLK CySYSCLK 6.000 MHz 6.000 MHz N/A
LCD_Clock(FFB) LCD_Clock(FFB) 3.000 MHz 3.000 MHz N/A